Todd Vierra
Todd brings more than 25 years of engineering and technical sales expertise in chip design, electronic design automation, and intellectual property. He joined BrainChip from ARM, where he was director of field sales engineers for more than 15 years, providing support for ARM processors in the Machine Learning, Internet of Things (IoT), embedded and automotive, client/mobile, and enterprise business divisions. He spent nearly seven years in high-speed ASIC design at Applied Micro Systems, and 4 years at Cadence Design Systems. At Nurlogic Design Inc., and Artisan Components Todd led the technical sales teams for digital and high-speed Analog IP. He has a BS Electrical, Electronics, and Communications Engineering and an MBA from Coleman University.
Martin Schofield
Martin has held senior financial crime prevention roles and is a well-known and established figure in the financial crime prevention sector. Martin is regarded as a highly competent consultant/adviser as well as an outstanding trainer, and a true expert in the field of financial crime prevention.
Over the last 21 years Martin has been engaged on numerous projects, both global and domestic for major financial services firms, involving policy authoring, reviews, audits and pre and post regulatory visit reviews and monitoring as well as the design and delivery of staff and management training in all aspects of financial crime prevention.
Richard Blann
Richard Blann is Head of Group Litigation & Conduct Investigations Legal at Lloyds Banking Group where he advises senior management on litigation strategy and tactics. He manages a broad portfolio of high value/high profile claims in the UK, US and beyond, supports significant internal investigations, and advises on financial crime. He also leads the Group’s Data Litigation team.
Prior to joining Lloyds in 2010, Richard worked in private practice conducting cross-border investigations and high value multi-jurisdictional litigation in the courts of a variety of jurisdictions for financial institutions, corporates and professional services firms.
Dolores Cassidy
Dolores Cassidy, B.Sc. Ph.D., graduated from University College Dublin with a Ph.D. in Physical Chemistry. In 1998 she joined the Intellectual Property Office of Ireland as a Patent Examiner, with particular responsibility for the examination of Supplementary Protection Certificates (SPCs). In 2021 she was promoted to the position of Head of Patent/SPC Examination at the Irish Office.
Srini Kakkera
Rohan Darole
Rohan Darole is a ML Product Specialist at Cadence TIP (Tensilica IP Group). He received his Master’s in Computer Science from SUNY-UB, Buffalo, NY. Rohan is leading a team of application engineers responsible for definition, realization, and customer engagements of Tensilica AI MAX Product Family. Previously he has worked on CV/ML Acceleration with Vision DSPs, Imaging (ISP) & Video Codecs SW Development.
Michael Hubrig
Michael is Sr. Architect in the Tensilica Central Applications Team. His team provides deep technical support for Vision and AI DSP and engines. Michael has 20 years of experience porting imaging and vision algorithms to DSP platforms.